The present invention firstly relates to an integrated DRAM memory cell according to the precharacterizing clause of claim 1. The invention also relates to a DRAM memory.
DRAM (Dynamic Random Access Memory) memory cells and memories represent an important type of memory for storing digital information. A DRAM is a memory in which data can be stored after inputting an address and can be read out again under this address. In DRAM memory cells or memories, respectively, the information is not stored as a switching state of a circuit but as a charge quantity in a capacitance. Such a memory cell can thus be formed with only one storage capacitor and one selection transistor. An example of a DRAM memory cell is shown in FIG. 1. Since each capacitor has leakage currents and leakage currents also flow via the selection transistor, the information in the DRAM memory cell is continuously reduced. The information content of the memory cell is therefore lost with time. In order to avoid this, the contents of the memory cells are periodically read out, the memory contents are evaluated and the memory cell is written to again. This means that the charge contents of the storage capacitors are refreshed again.
DRAM memory cells are usually connected together to form memory cell arrays, a DRAM memory having one or more such memory cell arrays. As a rule, only a limited area, which is called cell area and has an essentially rectangular configuration, is available to form the individual memory cell components (storage capacitor and selection transistors. The cell area usually has a greater extent in the longitudinal direction (longitudinal extent) than in the width direction (lateral extent). The individual components of the memory cell or, respectively, of its individual component parts are, as a rule, arranged approximately in a line and at a certain distance from one another behind one another within the boundary of the cell area. The resultant extent of the memory cell and thus also of the cell area is understood to be the longitudinal extent or extent in the longitudinal direction, respectively. The resultant extent of the memory cell in the perpendicular direction thereto, and thus also of the cell area, is understood to be the lateral extent or, respectively, extent in the lateral direction. Each memory cell is wired or can be wired to the cell periphery via a word line and a bit line, the word line and the bit line being conducted over the memory cell and being at least essentially oriented perpendicularly to one another. Such a configuration of the memory cell is shown by way of example in FIG. 1. By activating a certain word line, all memory cells connected to it can be read out, written to or refreshed with respect to their information content via their bit lines.
An essential feature of the DRAM development is the miniaturization of the patterns. On the one hand, the minimum pattern size F to be generated lithographically is reduced in size approximately by a factor of 1/{square root over (2)} from generation to generation. On the other hand, the architecture of the memory cell is changed in such a manner that the consumption of area per bit drops.
The bit line wiring of the individual cells establishes a grid into which read/write amplifiers also have to be introduced. The basic task of read/write amplifiers is to evaluate and amplify signals read our of the bit lines.
The area needed for the total wiring per memory cell defines a minimum size for the cell area up to which a reduction in size of the memory cell architecture leads to a saving in area. Dropping below this minimum cell size would mean that the space requirement of such wiring is fixed by the wiring grid and thus independent of the cell size achieved or achievable.
In the so-called xe2x80x9cfoldedxe2x80x9d bit line architecture hitherto used as is shown, for example, in FIG. 4 and will be explained in greater detail in the description of the figures, the minimum area needed for the wiring per cell is 8 F2. This can also be seen, for example, in FIG. 2. In the xe2x80x9cfoldedxe2x80x9d bit line concept, the individual bit lines are in each case arranged next to one another. This requires two bit lines in each case, namely a bit line BL to be evaluated and a reference bit line BBL. The reference bit line BBL has the task of comparing a signal read out of the bit line or, respectively, memory cell to be evaluated, with a reference value. This will be explained by means of a brief example.
In the DRAM memory cells, digital information can be stored, for example, in the form of logical xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. To each of these logical information items, a certain voltage value is allocated. For example, the voltage value for a logical xe2x80x9c0xe2x80x9d can be zero volts, whereas the voltage value for a logical xe2x80x9c1xe2x80x9d is, for example, 2 volts. Before the memory cell is read out, a reference voltage is applied to all bit lines, for example a voltage of 1 volt. When the memory cell is read out, the voltage value will either increase or decrease, depending on the information content of the memory cell. This change in voltage is compared with the reference voltage of 1 volt which is still present in the reference bit line. If the voltage value in the bit line to be evaluated is higher than the reference voltage value, the information content logical xe2x80x9c1xe2x80x9d was written in the memory cell. If the voltage values are smaller, the information logical xe2x80x9c0xe2x80x9d was written in the memory cell. The voltage signal read out of the bit line to be evaluated and of the reference bit line is conditioned and processed further, for example amplified in the read/write amplifier.
In the xe2x80x9cfoldedxe2x80x9d bit line concept, two word lines WL are conducted over each memory cell. One word line activates the selected cell whilst leaving the neighbouring cells, and thus the neighbouring bit line, deactivated. The second word line only passes the cell to be read out and activates the neighbouring cells when selected. A wiring architecture comprising one bit line BL and two word lines WL conducted in parallel over the memory cell needs an area of at least 8 F2 as shown in FIG. 2. The xe2x80x9cfoldedxe2x80x9d bit line concept is thus only appropriate for cells xe2x89xa78 F2.
Above the 4-Gbit generation, the architecture of the DRAM memory cell requires an area consumption of less than 8 F2. The wiring must then be changed in such a manner that it does not determine the space requirement of the cell array. This is achieved by conducting only a single word line over each cell. This is shown, for example, in FIG. 3. As can be seen from this figure, the minimum space requirement for the wiring drops to 4 F2. The consequence for the bit line architecture is a transition from the xe2x80x9cfoldedxe2x80x9d to the so-called xe2x80x9copenxe2x80x9d bit line concept. Such an xe2x80x9copenxe2x80x9d concept is shown, for example, in FIG. 5 and will be explained in greater detail in the description of the figures. As can be seen from FIG. 5, the grid of the read/write amplifier SA is reduced from 8 F to 4 F with a conventional word line and bit line arrangement, independently of the size of the memory cell. The grid is reduced abruptly which means that this grid is required for each cell which is  less than 8 F2 regardless of whether it is a 7 F2, 6 F2, 4 F2 cell or the like.
As can be seen from FIGS. 4 and 5, the grid of the read/write amplifier (SA grid) is determined by, among other things, the width of the bit line BL, the distance between the bit lines and by the arrangement of bit line BL and reference bit line BBL.
For cells  less than 8 F2, only a single word line WL can be supplied per cell. As a consequence of this, the neighbouring cells are also read out and the neighbouring bit line cannot be used as reference bit line as was possible in the xe2x80x9cfoldedxe2x80x9d bit line concept shown in FIG. 4. Instead, a bit line BBL from a neighbouring cell array is used as reference bit line. This results in the xe2x80x9copenxe2x80x9d bit line concept and the SA grid is abruptly reduced from 8 F to 4 F independently of the cell size.
In conventional bit line architectures, the distance between adjacent bit lines results from the orientation of the bit line in the direction of the longitudinal extent of the cell as can be seen, for example, in FIG. 1. The distance between two adjacent bit lines is thus fixed by the width of the memory cell. The width of the memory cell, in turn, corresponds to the minimum possible value of 2 F which results from 1 F pattern width of the memory cell components and 1 F distance from the adjacent memory cells.
Along the way to the so-called xe2x80x9ctrench cellsxe2x80x9d with architectures of  less than 8 F2, the distance between deep trench and gate is reduced. A deep-trench capacitor is a cylindrical capacitor which is aligned perpendicularly to the surface of the substrate in an integrated circuit. The gate is, for example, the gate of the selection transistor. If the distance between the storage capacitor and gate is reduced, the storage cell is correspondingly reduced in size in the longitudinal direction which can be seen, for example, in FIG. 1. Since the bit line is aligned or oriented in the longitudinal direction of the memory cell, the bit line distance between adjacent bit lines therefore remains constant independently of a reduction in size of the cells.
The abrupt reduction of the bit line grid and thus of the read/write amplifier grid from 8 F to 4 F presents problems, especially in the xe2x80x9copenxe2x80x9d bit line architectures. The reason for this is, among other things, that the layout of the read/write amplifier in the grid, reduced to one half, with planar transistors from which it is built up, is very difficult.
It is, therefore, the object of the present invention to provide a DRAM memory cell and a DRAM memory having a corresponding DRAM memory cell wiring in which the disadvantages described are avoided. In particular, it should be made possible to miniaturize memory patterns in transition from the xe2x80x9cfoldedxe2x80x9d to the xe2x80x9copenxe2x80x9d concept without abruptly reducing the grid of the read/write amplifiers by a considerable degree in the manner described above.
According to the first aspect of the present invention, this object is achieved by an integrated DRAM memory cell comprising a storage capacitor and a selection capacitor which are formed in the area of an at least essentially rectangular cell area, the cell area having a greater extent in the longitudinal direction than in the width direction and which is wired or can be wired to the cell periphery via a word line and a bit line, the word line and the bit line being conducted over the memory cell and being at least essentially oriented perpendicularly to one another. According to the invention, the DRAM memory cell is characterized in that the bit line is oriented perpendicularly to the longitudinal extent of the memory cell in the direction of the lateral extent of the memory cell.
In this manner, a bit line architecture is created by means of which an unstressed read/write amplifier grid for DRAM memory cells of  less than 8 F2 can be achieved.
The fundamental idea for solving the problem described above (the severe abrupt reduction of the read-write amplifier grid from 8 F to 4 F on transition from xe2x80x9cfoldedxe2x80x9d to xe2x80x9copenxe2x80x9d bit line concept) consists in arranging the bit line perpendicularly to the longitudinal direction of the cell. The bit line grid resulting from the combination of individual DRAM memory cells to form a DRAM memory, and thus also the read/write amplifier grid, now becomes a function of the longitudinal extent of the memory cell. This is explained in greater detail below with regard to the DRAM memory according to the invention. In addition to the advantages, effects and operation of the DRAM memory cell according to the invention, reference is, therefore, also made to the full content of the subsequent explanations relating to the DRAM memory according to the invention. The read/write amplifier grid scale now changes linearly with the longitudinal extent of the memory cell. As a result, the layout problem of the read/write amplifiers which has hitherto existed and is described above can be reduced.
Advantageous embodiments of the DRAM memory cell according to the invention are obtained from the subclaims.
The DRAM memory cell can advantageously have a cell area of  less than 8 F2. By means of the present invention, 7 F2 cells, 6 F2 cells and the like can be preferably achieved.
The bit line and/or the word line can advantageously have a width of 1 F.
The width of the memory cell is preferably 2 F whilst the memory cell preferably has a cell length of  less than 4 F.
According to the second aspect of the present invention, a DRAM memory is provided which has a number of DRAM memory cells according to the invention as described above. The memory cells in each case form one or more memory cell arrays, in each case a number of memory cells of a memory cell array being connected to a common word line and a common bit line, the word lines forming a word line grid and the bit lines forming a bit line grid.
In addition to the advantages, effects and operation of the DRAM memory according to the invention, reference is also made to the full content of the above explanations relating to the DRAM memory cell according to the invention.
The individual bit lines of each cell are now oriented perpendicularly to the longitudinal alignment of the memory cell, i.e. perpendicularly to its longitudinal extent and parallel to its lateral extent. If then the length of the memory cells is reduced, for instance by reducing the distance between the gates of the selection transistors and the storage capacitors, this reduction in distance also becomes noticeable in the distance between adjacent bit lines so that these move closer to each other to the degree of the shortening of the memory cell. In this process, the degree of reduction in distance is flowing, however, and not abrupt as in the transition from the conventional xe2x80x9cfoldedxe2x80x9d to the conventional xe2x80x9copenxe2x80x9d bit line architecture explained in the introduction to the description.
Advantageous embodiments of the DRAM memory according to the invention are obtained from the subclaims.
The DRAM memory can advantageously have an xe2x80x9copenxe2x80x9d pattern. Such a pattern takes into account the continuing miniaturization of the DRAM memories in the manner described above.
In this context, a bit line from another memory cell array can be used as reference bit line for the bit line of a memory cell to be read out.
The bit line grid is advantageously formed as a function of the longitudinal extent of the memory cells. This has the abovementioned advantages.
Apart from the components described before, the DRAM memory has, as a rule, one or more read/write amplifiers which, for evaluation and further processing of the signals transmitted via the bit lines, is/are wired to the latter. A read/write amplifier has the task of amplifying the signals passing via the bit lines which usually only have very small signal values, to the signal values required in each case for further usage steps.
The read/write amplifiers are preferably arranged in a grid corresponding to the bit line grid so that the grid of the read/write amplifiers varies linearly in scale with the longitudinal extent of the memory cells. This is illustrated, for example, by the following formula which is:       SA    ⁢          xe2x80x83        ⁢    grid    =                    2        ·        BL            ⁢              xe2x80x83            ⁢      grid        =                  2        ·                              cell            ⁢                          xe2x80x83                        ⁢            size                                2            ⁢            F                              =                        cell          ⁢                      xe2x80x83                    ⁢          size                F            
where SA grid=read/write amplifier grid, BL grid=bit line grid and F=minimum lithographic pattern size.
In each case a number of gates, in particular four gates, of adjacent memory cells can be advantageously connected to one another in the manner of islands via a word line.
In this manner, a particularly advantageous arrangement of the word lines, the totality of which forms a word line grid, can be implemented perpendicularly to the bit lines or, respectively, the bit line grid. The gates are, for example, gates of the selection transistors provided in each memory cell.
This word line can be advantageously formed as polysilicon line.
These word lines which in each case connect adjacent memory cells to one another in the manner of islands are, in turn, connected to a further metal word line at certain intervals so that the individual islands, especially the polysilicon islands, are connected to one another via the metal word lines in the individual memory cells.
The two word lines in the DRAM memory are preferably arranged above one another.
To ensure that in each case only one memory cell is read out on to each bit line, two metal word lines running next to one another can alternately in each case contact memory cell gates of different types. An example of this is shown with regard to FIG. 6.
To implement the islands, the word lines connecting adjacent memory cells in the manner of islands must be conducted over the respective source-drain region of the memory cell(s) which connects the storage capacitor, for example the deep-trench capacitor, to the selection transistor.
In the text which follows, a possible production variant is described for this. The isolation required when conducting the word lines over the source-drain regions can be implemented, for Example, via a so-called STI (Shallow Trench Isolation) process which, however, requires an additional photolithographic plane. The STI method is a trench isolation method in which adjacent transistors or other active regions of an integrated circuit are laterally isolated by trenches, the trenches being etched into monocrystalline silicon and being filled with insulating material,
To produce the abovementioned pattern, for example, first the gate of the selection transistor can be produced, for example via a suitable gate-oxide and gate-poly and gate-nitride deposition. After that, the gate is patterned. This is followed by the STI etching and the subsequent filling of the etched areas with oxide. The pattern can then be polished by means of a suitable CMP (Chemical Mechanical Polishing) method. The island-like connection of gates of adjacent memory cells is then produced via a word line, for example a polysilicon word line, in that the individual polysilicon islands are deposited at the required places and patterned via an additional photolithographic plane.
In summary, the DRAM memory cell according to the invention and the DRAM memory according to the invention and the resultant new memory cell and bit line architecture exhibit a number of advantages. For example, the read/write amplifier grid which varies in scale linearly with the longitudinal extent of the cells can be mentioned firstly. This also enlarges the bit line grid at the same time. This leads to a reduction in the disadvantageous coupling capacitances between adjacent bit lines which increase inversely to the distance between adjacent bit lines. To keep the resistance of the word lines low, the word line connecting the individual gates in the manner of islands, for example the polysilicon line, is contacted by a metal word line at certain intervals. In the area of these contacts, the distance between the bit lines must be correspondingly enlarged. These contacts can be made without additional space requirement in the bit line architecture resulting from the invention. The frequency of contacting is much greater than in conventional bit line architectures. This thus reduces the word line resistance.